Since 1995 the name ‘ALS’ has become synonymous with high-quality printed circuit board design. As the largest Cadence Allegro design bureau in the UK, ALS is able to take on the most challenging projects and still meet tight deadlines.

There exists a growing trend to outsource engineering tasks to centres of excellence – PCB design and signal integrity analysis are good examples of this practice. The high costs of CAD tools, maintenance and staff training make a good case for this approach. However, handing over your latest concept to a design bureau is not a decision to be taken lightly.

This is where ALS comes in. We have a long history working with some of the biggest names in the electronics industry, and have vast experience working with engineers and project managers who favour the ‘outsource’ model. Our broad customer base that spans consumer electronics, broadcast, data storage/networking, military/aerospace, motor sport and medical is testament to our experience in a diverse range of technologies.  

To find out how your projects can benefit from our services, This e-mail address is being protected from spambots. You need JavaScript enabled to view it us today!

Value Added

You will find other PCB design bureaus... but you will not find another PCB design bureau like Advanced Layout Solutions. This is because we provide not only PCB design, but signal integrity analysis too. Used in combination, we can not only design a great printed circuit board, but perform verification that your design will work electrically too. For clients who depend on their high-speed digital designs working on the first iteration, this approach is absolutely vital.

Furthermore, our close relations and partnerships with PCB fabricators and assembly houses mean that we can offer a complete prototype procurement service, for clients who wish to maximise the benefits of outsourcing.

What is Signal Integrity Analysis?

Preserving signal integrity (SI) at the printed circuit board level has become increasingly important over the past fifteen years. This is primarily due to the faster switching rates and lower noise margins common in today's integrated circuits.The demand for signal integrity analysis has given rise to many new tool offerings from CAE software vendors, including Cadence Allegro PCB SI (Specctraquest), Mentor Hyperlynx, Mentor ICX, Agilent ADS and Ansys Ansoft. These powerful tools allow the user to accurately predict how a printed circuit board will perform once assembled and running high-speed signalling. Further evidence of the demand for signal integrity analysis has been the popularity of seminars and training courses run by industry experts such as Howard Johnson, Eric Bogatin, Lee Ritchie, Doug Brooks and Rick Hartley. In the quest for 'right-first-time' design, the use of signal integrity analysis tools and techniques is a must for all high-speed digital designs.

What Sort of Designs Require Signal Integrity Analysis?

SI analysis was often considered necessary for designs employing sub-nanosecond edge rates. This rule of thumb means it is necessary for virtually all digital designs today. However, good examples of candidates for SI analysis are:

High-speed memory controllers/interfaces

Memory technologies such as double data rate DRAM (DDR, DDR2, DDR3, GDDR, etc) require great care in their implementation. SI analysis ensures that matched propagation delays, jitter, crosstalk and signal quality requirements are all preserved. The analysis also allows the exploration of different routing styles and termination scheme to achieve the best possible performance. Where applicable, memory vendors, such as Micron, Samsung, etc, even provide separate IBIS models describing the component's behaviour under different on-die termination (ODT) settings.

Multi-Gigabit serial links

High-speed serial links have gained popularity in recent years as a replacement for wide source-synchronous buses (the most obvious example being the replacement of PCI with PCI-Express) . The high-speed serialiser/deserialiser (SERDES) transceivers required to support these serial links are now common place in off-the-shelf FPGAs, most commonly the RocketIO found in Xilinx's Virtex devices and the HSSIO found in Altera's Stratix devices. However, these links operate in the gigabit-per-second range and the channel must be able to carry small signals well into the GHz range. At these frequencies losses from vias, trace lengths, trace widths, dielectrics, etc can all have an effect on signalling. For this type of analysis tools are required that can simulate the channel in the frequency domain and predict the bit-error rates (BERs) likely to be suffered by the channel.