Frequently Asked Questions
	There are many questions that we get asked time and time again by customers new to our way of working. We have listed some of the most common below, along with our response.
	Q: What is ODB++?
	A: ODB++ is the most intelligent CAD/CAM data exchange format available today, capturing all the CAD and fabrication data in one file. Previously the data package sent to the manufacturer would consist of a number of Gerber files, an aperture list, drill file and test data. Valor ODB++ format, on the other hand, is a single file which contains all the data required by the manufacturer to build your board. This allows manufacturers to load data more quickly, as there is no translation of data required, and more accurately than before.
	Q: At What speed would you consider a "high-speed" design approach should be used? I am using 133MHz devices - these don't seem very fast these days.
	A: A high clock rate implies a fast rising edge on your signals. Other than that, there is no connection between clock rate and signal rise time (edge rate). The important relationship is how long your traces are compared to the "length" of the signal's wavefront. If you are using sub-nanosecond edges (and you will be on a new logic board!) then, if your traces are longer than an inch or so, you are designing a high-speed digital system. Irrespective of how fast you clock the system, your will suffer from signal integrity issues when using fast edge rate ICs. At 133MHz clock, you have a huge 7.5ns clock period. However, your signals will transition in a tiny fraction of this time and without controlled impedance PCBs, correct termination, correct routing, etc. you are wide open to be hit by an SI artefact.
	Q: Can IBIS models be relied upon at very high speeds ?
	A: Maybe - All simulation work is dependant upon the quality of the I/O models stimulating the traces. A good IBIS model that has close correlation to real-world measurements can be heavily relied upon.
	Q: Presumably signal integrity doesn't concern our designs as we're only running at slow clock rates?
	A: Most signal integrity problems are a function of edge rate, that is, the rise (or fall) in signal voltage as a function of time. Although a high clock-rate implies a fast edge-rate, the inverse is not true. Over time, as silicon vendors shrink their die to reduce costs, the edge rate of an IC's output will increase. If you buy a 233MHz memory device and run it at 16MHz you will likely be using a signal rise time much faster than necessary and will therefore suffer many of the same SI issues as a 233MHz implementation.
	Q: Will 8mils of spacing on my traces control crosstalk adequately?
	A: Crosstalk is indeed proportional to distance between conductors, but it is also a function of edge rate. A constraint of 8mils trace to trace is a very harsh design rule to apply to a layout. To be cost effective, we are trying to pack the routing as densely as possible on as few layers as possible. Running simulations is the only way to reliably evaluate where a crosstalk risks exist. Furthermore, traces that run in parallel for large distances tend to be bits of the same synchronous bus. In this case crosstalk between the signals is somewhat irrelevant as the effects occur in the common settling time when the device inputs are not sensitive.
	Q: Is the 10mils of trace matching given in the design guide necessary?
	A: Consider that 10mils of matching. Taking a rough propagation delay of 170ps/inch, 10 mils represents 1.7ps! For even a 1Gbps signal this is matching to 0.17% of the data eye! Bear in mind that an 0402 resistor is 40mils x 20mils, there is more than 10 mils between the edge  and the center of the resistor pad itself. In short, hopefully you don't need anywhere near 10mils of matching between bits of a bus for your design to work. The tools will help you achieve it but it's added time and cost that almost certainly won't give any gain. A more realistic matching figure is 10% of rise time. Following this guide a 'fast' 100ps edge would only require matching to 60mils; a 1ns edge would require 600mils, or 0.6inches. Also bear in mind via delay as it is nonsensical to match traces to a few mils and ignore this. ALS takes via delays into account when matching signal propagation. A signal on a PCI plug-in card with four vias could have 0.25 inches further to travel than a signal with no vias!
	Q: Can signal integrity analysis really reduce time to market?
	A: Certainly. PCB re-spins have historically been due to connectivity errors, usually typos at the schematic level. Re-spins today are commonly performed to fix electrical issues caused by high-speed signaling, changing the PCB but not the necessarily the schematic. The benefits of using simulation to detect such problems early on can not be overstated. Interestingly, running simulations also often identifies traditional connectivity errors at the schematic level too, because if it's not connected - it can't be simulated.
	Q: Can any useful simulations be run prior to schematic design?
	A: Yes - Pre-route simulation is all about running simulations on theoretical traces, vias, connectors and I/O models. It is an exploratory design stage and tests out the "what if" scenarios.
	Q: Can EMC problems be reduced through simulation?
	A: Yes - If you look after signal integrity you will inadvertently help EMI emissions by reducing the amount of uncontrolled energy in the system.
	Q: Can crosstalk be measured using simulation?
	A: Yes - During a crosstalk simulation the tool will identify potential coupling problems. It will then build a model of the coupled traces, stimulate the aggressors and measure the crosstalk voltages picked up on the victim nets.
	Q: Can transistor models be used to describe I/Os instead of IBIS?
	A: Yes - HSPICE models can be used in our design flow. Using transistor-level models also allows us to model data dependant characteristics (such as pre-emphasis) commonly found in MGHz SERDES I/Os.
	Q: How are high-frequency trace effects modeled in Allegro ?
	A: All simulation tool that ALS use model high-frequency trace phenomena. Skin effect, proximity effect and dielectric (heating) loss result in an apparent linear resistance along the length of a trace. In an analogue circuit this gives rise to an amplitude attenuation. In a digital circuit it causes a reduction in signal rise-time. These are collectively referred to as "lossy" simulations.
Advanced Layout Solutions Ltd offers the complete PCB design solution.
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