| Tools |
|
For successful PCB design, you need the right tools for the job. At ALS we continually invest in new, fully maintained CAD tools and computer systems. Printed Circuit Board Design In order to efficiently design a complex printed circuit board, you must be an expert in the use of your design tools. At ALS we believe that this requires focus on a single design environment, in our case the Cadence Design Systems' "Silicon-Package-Board" tool flow. The printed circuit board design tool in this flow is the award winning "Allegro PCB Editor" system. At ALS we own, maintain and run many seats of this tool and use it exclusively for all our PCB design effort. Schematic Design We can undertake schematic design entry using either “Cadence Design Entry HDL” (formerly known as "Concept") or “Cadence Capture CIS” (OrCAD). The recent integration of the OrCAD schematic tools under the Cadence banner has enabled OrCAD users to develop their systems to allow many new rules and directives to be passed seamlessly from the schematic through to our Allegro design systems. These new features will bring you many benefits including: • Reduced hand written constraint documents • Full forward and back annotation • Full gate & pin swapping • Incremental netlisting • Increased data integrity of future modifications Signal Integrity Tools Advanced Layout Solutions is focused on the Cadence PCB design flow. For this reason the tools used for SI analysis must work in harmony with the Allegro design database. The natural choice for our simulation environment is therefore “Allegro PCB SI” which provides the simulation capabilities necessary for the majority of analyses. For high-speed applications in the gigabit-per-second regime, Agilent Technologies' ADS (Advanced Design System) is used. Key advantages of Allegro PCB SI: • IBIS 4.0, DML and encrypted HSPICE model support • Advanced field solver models frequency-dependant phenomena (Dielectric loss, skin effect and crowding all taken into account) • Extensive sweep simulations of virtually any trace parameter • Coupled trace models for crosstalk simulation • Random data pattern stimulus for inter-symbol interference (ISI) analysis • Ability to take in designs from both Cadence Design Systems and Mentor Graphics • Same environment for both simulation and layout Direct model binding and extraction to and from PCB Layout • Static IR-drop Analysis • Supported model formats are DML, IBIS (2.1, 3.2, 4.0), ESPICE, QUAD, S-Parameter (Touchstone) and HSPICE. For more information on Allegro SI - click here Where RF or S-Parameter extraction are the nature of a simulation the Agilent Technologies' “Advanced Design System” is the tool of choice. This tool set allows very accurate modelling of complex PCB structures, making it ideal for analysing detailed features (such as via stubs) in the frequency domain. This tool directly links into the Allegro PCB Editor.
For more information on Agilent ADS - click here
Where buffer models are supplied in transistor-level HSPICE format, Advanced Layout Solutions uses the the “Synopsys HSPICE” simulation engine for maximum accuracy.
For more information see www.hspice.com Design For Manufacture There are many reasons why a design, even when fully checked on a CAD system, can fail when the data is presented for manufacture. To overcome such issues and to provide a smooth transition of your boards through manufacture we have invested in multiple “Valor Enterprise 3000” systems that enable us to pin point any manufacturing issues on your design before the data leaves our company. Valor ODB++ format is becoming the de facto standard for passing data between design houses and manufacturers. Unlike Gerber, this Valor format provides all the data required to manufacture your board in a single file archive. Additionally, unlike many CAD systems that simply output a Valor ODB++ file, we provide you with verified ODB++ files. By verifying the data within the ODB++ file we ensure that the physical board data that is being used for manufacture matches the connectivity of the design exactly. ![]() |






