This graphic illustrates that the cost of
fixing an error escalates as the design process continues. Errors found at
final testing can mean a major re-design and long delays in bringing a
product to
market. Errors found early in the cycle are relatively easy to correct and
have a minimal effect on the timescale. At ALS, signal integrity analysis is
available at every stage of the design flow. The net result: a more robust product
delivered in less time at less cost.
Pre-Route
Simulation
We offer access to the SI tools at the
pre-route stage (even pre-schematic!) for product feasibility studies.
This type of analysis includes
exploratory simulations to evaluate topologies, identify design constraints
and determine stack-ups. We can evaluate IO capabilities and
determine trace
lengths, impedances, termination values etc.
Concurrent Simulation.
Once placement and routing are underway
simulations can be run to verify the routing strategy at an early
stage. Here we are checking that the actual interconnect does
not adversely affect the pre-route simulation results.
Post-Route Simulation
Once complete an enormous amount of data can
be generated and reported back to the customer. These reports form
a sign-off status for the finished design files, detailing
parameters such as crosstalk, propagation delays, first switch times, final settle
times, overshoot, noise margin, characteristic impedance, buffer
delays, slew rates to name but a few.
"Virtual Debug"
If you have SI problems with existing hardware
the simulation tools can be used to identify the root-cause of the
problem. Once identified, the tools can be used to experiment with
possible fixes and modifications to avoid extremely time consuming
rework-lab modifications.
All simulation work can be carried out as an
"on-site" service.