Printed Circuit Board Design
Schematic Design
We can undertake schematic design entry using either Cadence Design Entry HDL (formerly known as "Concept") or Cadence Capture (OrCAD). The recent integration of the OrCAD schematic tools under the Cadence banner has enabled OrCAD users to develop their systems to allow various rules and directives to be passed seamlessly from the schematic through to our Allegro design systems.
With board design complexity growing almost daily, it is now more important than ever to ensure you are able to accurately pass circuit properties and gate & pin swapping attributes through to design. By adding properties to a schematic you can avoid the reams of instructions that accompany today's designs. This also means that the design rules become embedded in the layout, identifying the routing that was "by design" and thus avoiding potential problems during rework.
The introduction of gate & pin swapping into your schematic parts allows the quick re-synchronisation of the netlist to suit the component placement. This is particularly useful where high I/O count FPGA's are being used. Any changes to the connectivity can then be fed back into your OrCAD schematic automatically.
This new strategy will bring you many benefits including:
- Reduced hand written constraint documents
- Full forward and back annotation
- Full gate & pin swapping
- Incremental netlisting
- Increased data integrity of future modifications
Advanced Layout Solutions is focused on the Cadence design flow and for this reason Allegro® PCB SI™ is the natural choice for our simulation environment.
Key advantages of Allegro® PCB SI™
There are times when it is appropriate to use transistor-level HSPICE® models for board-level simulations. In these situations Advanced Layout Solutions use the Cadence tool-set to target the Synopsys® HSPICE® engine for maximum simulation accuracy.
For more information see www.hspice.com
Allegro® PCB SI™At first glance the simulation environment looks identical to Allegro PCB Designer - such is the high level of integration between the tools in the Cadence flow.
Constraint
Manager
The Constraint Manager ensures that physical
and electrical constraints are met. There's an endless list of
electrical parameters available for the design engineer to
control, from
overshoot (mV) to first switch times (ns).
SigXplorer
Whether we're running pre, concurrent or
post-route simulations, the SigXplorer "canvas" is
the common space for exploring net topologies and identifying the
necessary constraints.
SigWave
Viewing simulation results in SigWave is the
natural way to study signals as they can be easily compared to real
measurements on oscilloscope displays.
Signals can be viewed in the time or frequency domain, eye
patterns can be displayed and data can be imported from Tektronics,
LeCroy, HP and Agilent laboratory instruments.
Model
Integrity
Simulation models can be developed,
modified, checked and translated using this tool. Supported
formats are DML, IBIS (2.1, 3.2, 4.0), ESPICE, QUAD, S-Parameter
(Touchstone) and HSPICE.
Design For Manufacture
Valor ODB++ format is becoming a defacto standard in passing data between design and board manufacture. Unlike Gerber, the Valor format provides all the data required to manufacture your board in a single file archive.
Additionally, unlike many CAD systems that simply output a Valor ODB++ file, we provide you with verified ODB++ files. By verifying the data within the ODB++ file we ensure that the physical board data that is being used for manufacture matches the connectivity of the design exactly.
What is ODB++?
See our frequently asked questions page...