High-Speed Serial Technologies

An increasing number of our customers are turning to high-speed serial technologies to avoid the almost impossible design constraints imposed by wide, high-speed synchronous buses. To support standards such as PCI Express™, IC vendors Xilinx and Altera both now include multi-gigabit serialiser /deserialiser (SERDES) IOs on their FPGAs.


The functionality of these multi-gigabit transceivers requires us to use 'IBIS-AMI' models for simulation. This simulation environment allows us to capture the minutiae of the SERDES unit, modelling drive strengths, pre-emphasis, receiver EQ, jitter, etc.


High Speed Serial



We have extensive experience modelling 3.125Gbps to 11Gbps SERDES channels…



• Xilinx Virtex II Pro RocketIO™
   Serial Transceivers

• Xilinx Virtex 4 to 7 Series RocketIO  
   GTP/GTX™ Serial Transceivers


  • Altera Stratix / Arria HSSIO Serial Transceivers 


"Our customers' ability to quickly design-in the Virtex II Pro Rocket IO technology is critical. Working with Cadence, we are minimizing the design-in time for our customers, enabling them to take advantage of dramatic system cost savings through the implementation of the serial technology in their next design." 

Rich Sevcik - senior vice president and general manager
of FPGA products at Xilinx.


“By delivering the first fully behavioral SERDES model, Altera customers implementing Stratix GX devices are able to proactively address link simulation issues typical of 3.125-Gbps transceiver designs. In Allegro PCB SI, our behavioral DML model performs at least 20 times faster than traditional transistor-level models without sacrificing accuracy.” 
Vipul Badoni - senior manager, high-speed I/O applications
engineering at Altera.



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